1. Technical Field
The present invention is directed generally toward data processing devices. More particularly, the present invention relates to a method and apparatus for testing an embedded hard macro in an integrated circuit chip utilizing a test wrapper that surrounds the inputs/outputs of the hard macro.
2. Description of the Related Art
Customers purchase individual integrated circuit (IC) chips to include in their own larger devices that they then sell. For example, a customer may purchase a processor from the processor's manufacturer and then include that processor in a device that is manufactured and sold by the customer. These customers depend upon the reliability of processing cores, memory chips, hard macros, and the other integrated circuits that they purchase to function properly; otherwise, the device the customer sells will fail. Therefore, the customer will typically test the individual IC chips, purchased from other suppliers, during the manufacturing process of the customer's device.
The customer may test each IC chip to verify that the circuitry in the chip is functioning properly. One standard way for testing chips involves using an external memory tester at the customer's manufacturing site. An external memory tester supplies test patterns to the chip to detect faults in the chips.
One example of testing is scan-based testing. A component in the chip, such as a hard macro, is equipped with an externally accessible scan chain. The testing consists of scanning into the scan chain in the hard macro a sequence of test data. The scan chain includes multiple latch registers coupled together in a serial manner. The test data is shifted serially through these latch registers allowing information to be serially passed into and out of the scan chain. The scan chain allows for external control and examination of individual states of the hard macro that includes the scan chain and that is being tested.
There are automatic test pattern generation tools that generate patterns based on the design of the device. The manufacturer of the hard macro will typically provide a sample test pattern that the customer may use to test the hard macro. However, the sample test pattern will not exercise the hard macro in precisely the manner that it is to be used by the customer because the manufacturer of the hard macro does not know where or how the hard macro is to be used. Thus, it is possible that undetected defects may exist within the hard macro.
In order to for the customer to completely test the hard macro at the customer's site, the customer needs access to the logic design of the hard macro. However, the manufacturer of the hard macro does not typically make this design public. Thus, the customer does not have access to the internal logic diagrams of the hard macro. Because the customer does not know exactly how the hard macro is designed, the customer is not able to perform sufficiently complete testing. The customer would need access to the hard macro's logic diagrams or code in order to produce a test pattern that would completely test the hard macro. This logic or code is not made available to the customer.
FIG. 1 is a block diagram of a system on a chip (SOC) 100 that is coupled to a tester 102 in accordance with the prior art. SOC 100 includes a hard macro 104, a processor core 108, a processing element 110, a processing element 112, and a hard macro 114. SOC 100 may also include additional cores, processing elements, hard macros, and/or other devices or components. Although they are not depicted in the figure, SOC inputs are received by and SOC outputs are generated by processor core 108, processing element 110, processing element 112, hard macro 114, and all other additional cores, processing elements, hard macros, and/or other devices or components that are included within SOC 100.
A system on a chip is defined as being a single integrated circuit chip that includes on it a processing core as well as all of the components that are needed by the processing core.
A hard macro is a particular set of instructions. These instructions can be implemented in hardware or in software. As depicted by FIG. 1, these instructions are implemented within a hardware device such as a single integrated circuit or chip 104. One or more scan chains are included in hard macro 104. The scan chains 106 are provided within macro 104 for testing macro 104. A scan chain is a serial path that shifts test data from one device in the chain to the next device located serially in the chain.
As depicted by FIG. 1, an external tester 102 may be coupled to SOC 100 in order to test devices within SOC 100 such as macro 104. Hard macro 104 receives serial test data from tester via scan signal SI 116. This test data is scanned into scan chains 106 in order to test hard macro 104. The results of the test performed on macro 104 using the input signal SI are serially scanned out as captured result data. The captured result data is serially scanned out of scan chains 106 and is provided back to tester 102 as a scanned out signal SO 118. Tester 102 can then analyze the captured data to determine whether hard macro 104 is performing as it should and whether it has any manufacturing defects.
Therefore, a need exists for a method and apparatus for testing a hard macro that is embedded within a system on a chip in an integrated circuit chip. The needed method and apparatus tests the embedded hard macro utilizing a test wrapper that surrounds the inputs/outputs of the hard macro in order to permit a customer to perform sufficiently complete testing of the hard macro.